An Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector

초록

This article presents a synthesizable digital low-dropout regulator (DLDO) that precludes the use of an output load capacitor. For efficient regulation, the DLDO consists of fine and coarse loops that have different load conditions to operate. The dual loops are made of typical standard cells to improve the synthesizability. In the coarse loop, a comparator (CMP)-triggered oscillator is employed to generate a high-frequency clock signal without concerning the metastability in the CMP. In order to achieve a fast response to a voltage droop caused by load–current variation, a droop detector and latch-based drivers are exploited that are capable of compensating for a voltage droop asynchronously. The prototype of the DLDO was fabricated in 28-nm CMOS technology. A range of supply voltage is from 0.5 to 1.0 V with a 50-mV dropout voltage. Depending on a supply voltage, a maximum load current and a quiescent current are measured as 160-to-480 mA and 7.7-to-241 $\mu$ A, respectively. While a load current is increased from 20 to 450 mA with a 2-ns edge time, a 112-mV voltage droop and a 1.4-ns response time are achieved. Thanks to the synthesizability and the output-capacitor-free design, the DLDO occupies an 0.049-mm ${}^2$ total area and offers 9.8-A/mm ${}^2$ current density. IEEE

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