Capacity Estimation for Semiconductor Wafer Fabrication Facilities via an Optimization Model Based on Flexible Lead Times

초록

In this paper, we consider the problem of production capacity estimation for a semiconductor wafer fabrication facility. Capacity estimation involves determining the maximum achievable throughput of a wafer fabrication facility during a given planning horizon in consideration of both product mix and target cycle time. The wafer fabrication facility (fab) is one of the most complex production systems, consisting of hundreds of process steps for each product as well as thousands of processing machines and re-entrant process flows wherein products must visit the same workcenter multiple times. In this regard, estimating production capacity by modeling the wafer manufacturing process is a challenging problem. To properly capture the dynamics of the process, we propose a flexible-lead-time-based optimization model that considers both the state of work-in-process (WIP) over time and the relationship between WIP levels and lead times. The results of simulation experiments using a real-sized instance demonstrate the advantages of the proposed model over existing alternatives.

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