A K-/Ka-Band Fully Integrated Stacked CMOS Power Amplifier with Capacitive Neutralization for 5G Millimeter-Wave Applications

초록

This paper presents a fully integrated three-stage stacked power amplifier (PA) operating in the K-/Ka-band, fabricated using a TSMC 65 nm CMOS process for fifth-generation (5G) millimeter-wave applications. To improve the output power without sacrificing reliability, a two-stacked-FET configuration is adopted in the power stage, which distributes the voltage stress across series-connected transistors and permits a higher supply voltage than a conventional cascode structure. A differential topology with capacitive neutralization is employed in both the common-source driver stage and the stacked power stage. The neutralization capacitance is determined from a stability- and gain-oriented analysis based on the Rollett stability factor (K) and the maximum available gain (MAG), which clarifies the trade-off between feedback cancelation and wideband gain flatness over the operating band. The fabricated PA occupies a total chip area of 0.51 mm2, including pads, with a core area of 0.18 mm2. The measurement results demonstrate a measured 3 dB bandwidth of 6.7 GHz from 24.6 GHz to 31.3 GHz, a peak small-signal gain of 32.9 dB, a saturated output power of 20.8 dBm, an output 1 dB compression point of 16 dBm, and a peak power-added efficiency of 20.4% at 28.5 GHz. Over the 26-30 GHz range in which the large-signal characterization was performed, the saturated output power varies by less than 1 dB and the efficiency by less than 2 percentage points, indicating that the combination of capacitive neutralization and stacked-FET operation provides a compact solution for wideband K-/Ka-band CMOS power amplification.

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