A study of the referenceless CDR based on PLL

Kim, J.H.; Hwang, Y.; Moon, Y.

doi:10.1109/ISOCC.2016.7799779

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A study of the referenceless CDR based on PLL

Kim, J.H.;
Hwang, Y.;
Moon, Y.

초록

Clock data recovery (CDR) circuit is an essential component for serial data communication. S/PDIF which is one of data coding is used. The CDR based on PLL recovers clock and data of 2.8224 24.576MHz and was designed with the frequency detector (FD) to detect the frequency by using the preamble. The PLL, frequency detector (FD) and the reset circuits were used to design the refernceless CDR based on PLL. 65nm CMOS process is used in this study. © 2016 IEEE.

제목: A study of the referenceless CDR based on PLL

저자: Kim, J.H.; Hwang, Y.; Moon, Y.

DOI: 10.1109/ISOCC.2016.7799779

발행일: 2016-10

학회명: 13th International SoC Design Conference, ISOCC 2016

개최국가: 대한민국

학회 개최일: 2016-10-23 ~ 2016-10-26

언어: ENG