FPGA Implementation of a Deterministic and Bit-Accurate Quad-Core Quad- Cycle Systolic Ensemble NPU for Edge Inference

초록

This paper presents the FPGA implementation of a deterministic and bit-accurate quad-core, quad-cycle systolic ensemble NPU for edge inference. The proposed architecture integrates four independent NPU cores operating under a fixed execution schedule and employs a systolic fully-connected computation stage to maintain a defined accumulation order across all cores. The design emphasizes reproducible numerical behavior and structural determinism in hardware inference. To validate numerical equivalence, hardware outputs were directly compared against a Python reference model. A total of 100 CIFAR-10 inference samples were evaluated, resulting in 1,000 final output comparisons using a fixed 32-bit signed representation. All hardware results matched the reference exactly without discrepancy. The implementation confirms that deterministic execution and strict bit-accurate consistency can be preserved from software modeling to FPGA deployment. The proposed architecture provides a reproducible and verifiable edge inference platform suitable for reliable embedded AI systems. Through this work, we impact the field of edge intelligence by providing a hardware-verified and bit-accurate systolic framework that ensures 100% reliability and reproducibility for critical embedded AI applications.

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