Suppressed Negative DIBL of Ferroelectric HEMT With Gate-Align Patterned AlScN Stack

  • Lee, Gyuhyung
  • Joo, Hyeong Jun
  • Oh, Seung Yoon
  • Yoo, Geonwook
Citations

WEB OF SCIENCE

1
Citations

SCOPUS

1

초록

In this letter, we present a ferroelectric GaN HEMT with gate-align patterned AlScN stack, suppressing negative drain-induced barrier lowering effect. The FeHEMTs exhibited apparent counterclockwise hysteresis with a steep SS even at high drain voltage by preventing unintended poling of ferroelectric polarizations induced by high negative gate-drain bias. Furthermore, the structure provides enhanced gate controllability with a steep subthreshold swing (SS) of 13 mV/dec and an increasing memory window depending on gate voltage sweep ranges. The results highlight the potential of employing the proposed FeHEMT for GaN-based logic circuits and energy efficient devices.

키워드

Logic gatesHEMTsEtchingMODFETsCurrent measurementBidirectional controlLeakage currentsHall effectWide band gap semiconductorsAluminum gallium nitrideHigh-electron-mobility transistors (HEMTs)ferroelectricAlScNself-aligned structure
제목
Suppressed Negative DIBL of Ferroelectric HEMT With Gate-Align Patterned AlScN Stack
저자
Lee, GyuhyungJoo, Hyeong JunOh, Seung YoonYoo, Geonwook
DOI
10.1109/LED.2025.3568428
발행일
2025-07
유형
Article
저널명
IEEE Electron Device Letters
46
7
페이지
1051 ~ 1054