2.4-GHz CMOS Power Amplifier With Common-Mode Self-Rejection Technique to Suppress Even Harmonics

초록

In this study, we propose a common-mode self-rejection (CMSR) technique to improve the linearity of CMOS differential power amplifiers. The proposed CMSR technique is implemented through a matching network consisting of a Guanella transformer between the driver and power stages of the differential power amplifier. The CMSR structure using the Guanella transformer serves as a matching network for the fundamental frequency and at the same time rejects even harmonics, thereby improving the linearity of the power amplifier. We design a 2.4-GHz differential power amplifier using a 130-nm PD-SOI CMOS process to verify the feasibility of the proposed CMSR technique. When a continuous wave signal is used, the P1dB and peak power-added efficiency (PAE) are measured as 25.51 dBm and 35.39% at 2.4 GHz, respectively. The second harmonic component in the low output power region and P1dB are -42.55 dBc and -55.4 dBc, respectively. When the 802.11n WLAN modulated signal of 64-QAM is used, the measured PAVG and PAE are 18.57 dBm and 15.97% under conditions where EVM is less than 3.98%, respectively. Additionally, when a 64-QAM LTE signal with a bandwidth of 20 MHz is used, the PAVG and PAE measured under the condition that the ACLR is less than -30 dBc are 20.33 dBm and 16.93%, respectively. The fabricated chip size is 2.6x1.3 mm(2), including test pads.

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