A study of low jitter phase locked loop for SPDIF

초록

CDR (Clock data recovery) circuit is an essential component for serial data communication. S/PDIF generates a lot of jitter from 2T and 3T. The PLL recognizes that the frequency changes in 2T and 3T portion. Change in frequency loses locking of the block. 3T detector reset Circuit is designed for reducing the jitter. Output jitter specifications of 9 frequencies are satisfied. 65nm CMOS process is used in this study. © 2017 IEEE.