Stegano-ECC: Enhancing DNN fault tolerance with embedded parity for important bits

초록

Recently, there has been increasing adoption of deep neural network (DNN) inference tasks directly on edge devices. These DNN inference tasks face critical reliability challenges due to increased DRAM errors caused by harsh operating conditions and resource constraints in edge environments. Though the conventional error correction codes (ECCs) mitigate DRAM errors exploiting parity bits, they incur substantial storage overhead, thereby making it challenging to deploy them on resource-constrained edge devices. In this paper, we propose Stegano-ECC, a novel error protection scheme for DNN inference on edge devices, which provides strong DNN fault tolerance against DRAM errors without storage overhead. Stegano-ECC selectively applies single error correction (SEC) codes only to the important bits (that have a significant impact on DNN inference accuracy) of DNN weights, improving fault tolerance during DNN inference. It embeds the parity bits of SEC codes within the relatively less important bits of weights, which avoids any storage overhead while minimizing the DNN accuracy degradation. Our evaluation results show that Stegano-ECC significantly improves fault tolerance by up to 500000x and 27778x in FP32 format (up to 2000000x and 10.0x in FP16 and INT8 format, respectively), compared to the conventional systems and the state-of-the-art error protection technique for edge environments, respectively.

키워드