상세 보기
FPGA based implementation of FAST and BRIEF algorithm for object recognition
객체인식을 위한 FAST와 BRIEF 알고리즘 기반 FPGA 설계
- Heo, H.;
- Lee, J.-Y.;
- Lee, K.-Y.;
- Lee, C.-H.
초록
In this paper, we implemented the conventional FAST and BRIEF algorithm as hardware on Zynq-7000 SoC Platform. Previous feature-based hardware accelerator is mostly implemented using the SIFT or SURF algorithm, but it requires excessive internal memory and hardware cost. The proposed FAST & BRIEF accelerator reduces approximately 57% of internal memory usage and 70% of hardware cost compared to the conventional SIFT or SURF accelerator, and it processes 0.17 pixel per clock. © 2013 IEEE.
- 제목
- FPGA based implementation of FAST and BRIEF algorithm for object recognition
- 제목 (타언어)
- 객체인식을 위한 FAST와 BRIEF 알고리즘 기반 FPGA 설계
- 저자
- Heo, H.; Lee, J.-Y.; Lee, K.-Y.; Lee, C.-H.
- 발행일
- 2013-06
- 학회명
- 2013 IEEE International Conference of IEEE Region 10, IEEE TENCON 2013
- 개최지
- Xi'an, Shaanxi
- 개최국가
- 대한민국
- 학회 개최일
- 2013-10-22 ~ 2013-10-25
- 언어
- KOR