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A delay estimation method using reduced model of RLC interconnects
- Park, C.-W.;
- Jeong, M.-S.;
- Kim, K.-Y.;
- Kim, S.-Y.
초록
This paper proposes a new method for delay time calculation in RLC interconnects. This method is simple, yet precise. The proposed method can calculate the delay time of RLC interconnects by simple numerical formula calculation without complex moment calculation using reduced model RLC interconnects. The results using the proposed method for RLC circuits show that the average relative error is within 10% in comparison with HSPICE simulation results. © 2008 IEEE.
- 제목
- A delay estimation method using reduced model of RLC interconnects
- 저자
- Park, C.-W.; Jeong, M.-S.; Kim, K.-Y.; Kim, S.-Y.
- 발행일
- 2008
- 학회명
- 2008 Electrical Design of Advanced Packaging and Systems Symposium, IEEE EDAPS 2008
- 개최지
- Seoul
- 학회 개최일
- 2008-12-10 ~ 2008-12-12