Modeling and description of semiconductor IP interfaces for system-level SoC design

초록

In system-on-chip (SoC) design, interface problems often occur in combining different intellectual properties (IPs) with different description methods, since interface description style of each IP has no consistency. In this paper, IP interface modeling and description guidelines are proposed to help IP integration in SoC design. IP interface are modeled based on 4 levels of abstractions, and data flows, blocks, ports, signals, modeling files, and description languages according to levels of abstraction. IP interface description includes 11 core items to provide important information to combine heterogeneous IPs. This guideline is very helpful and effective in IP integration, and it will contribute to semiconductor industry significantly.