A 1.8-GHz CMOS Power Amplifier Using Stacked nMOS and pMOS Structures for High-Voltage Operation

Son, Ki Yong; Park, Changkun; Hong, Songcheol

doi:10.1109/TMTT.2009.2031936

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A 1.8-GHz CMOS Power Amplifier Using Stacked nMOS and pMOS Structures for High-Voltage Operation

Son, Ki Yong;
Park, Changkun;
Hong, Songcheol

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12

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SCOPUS

18

초록

A class-E power amplifier is proposed in this study. It uses both nMOS and pMOS as switching devices to reduce the voltage stress of each transistor. A voltage-combining scheme with nMOS and pMOS is proposed, and a transformer is designed using this scheme. The power amplifier is implemented in a 0.18-mu m RF CMOS process. Measurements show a maximum output power of 30.2 dBm with 36.8% power-added efficiency at a 3.3-V supply voltage. The power amplifier sustains a supply voltage of up to 3.9 V.

키워드

Cascode amplifiers; CMOS; differential; power amplifiers; transformers; DISTRIBUTED ACTIVE-TRANSFORMER; LINE TRANSFORMER; 0.18-MU-M CMOS; EFFICIENCY; ARCHITECTURE; COMBINER

제목: A 1.8-GHz CMOS Power Amplifier Using Stacked nMOS and pMOS Structures for High-Voltage Operation

저자: Son, Ki Yong; Park, Changkun; Hong, Songcheol

DOI: 10.1109/TMTT.2009.2031936

발행일: 2009-11

유형: Article

저널명: IEEE Transactions on Microwave Theory and Techniques

권: 57

호: 11

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