Hybrid-Oxide Two-Stacked-FET CMOS Power Amplifier With Optimized Gate Impedance for X-Band Applications

초록

This paper presents a hybrid-oxide (HO) stacked-FET architecture aimed at enhancing the output power of high-frequency CMOS power amplifiers. In the proposed topology, a thin-gate-oxide transistor is employed as the common-source (CS) device, while a thick-gate-oxide transistor is used as the common-gate (CG) device within the stacked-FET configuration. By leveraging the distinct breakdown characteristics of each device, the proposed structure redistributes the voltage stress across the stack, enabling higher voltage swings while reducing the number of stacked transistors. The gate impedance control (GIC) capacitor is optimally designed to achieve the desired voltage distribution ratio without overstressing individual devices. A theoretical analysis is conducted to derive the optimal GIC capacitance required to ensure proper device operation under unequal voltage drops. A prototype power amplifier was implemented using a 65-nm bulk CMOS process. The fabricated chip occupies an area of 1.04 & times; 0.60 mm(2), with a core area of 0.90 & times; 0.26 mm(2). The amplifier operates over the 8-13 GHz frequency band and achieves an output 1-dB compression point (OP1dB) of 25.7 dBm and a peak power-added efficiency (PAE) of 26.5% at 10 GHz. Under a 64-QAM modulated input with 100 MHz bandwidth and 9.6 dB peak-to-average power ratio (PAPR), the amplifier delivers an average output power (P-AVG) of 17.1 dBm and average PAE of 8.4%, with an error vector magnitude (EVM) of-25 dB. These results demonstrate that the proposed architecture offers a promising design alternative for reducing complexity while maintaining high output power in RF CMOS power amplifier applications.

키워드