Low-power 32bitx32bit multiplier design with pipelined block-wise shutdown

초록

This paper proposes a novel low-power 32bitx32bit multiplier with pipelined block-wise shutdown scheme. When it idles, it turns off supply voltage to reduce both dynamic and static power. It shutdowns and wakes up sequentially along with pipeline stage to avoid power line noise. In idle mode, the proposed multiplier consumes 0.013mW and 0.006mW in 0.13 mu m and 0.09 mu m technologies, respectively, and it reduces power consumption to 0.07%-0.08% of active mode. As fabrication technology becomes small, power efficiency degrades in the conventional clock gating scheme, but the proposed multiplier does not. The low-power design methodology in this paper can be easily adopted in most functional blocks with pipeline architecture.