Scalable Van Der Waals Integration of III-N Devices Over 2D Materials for CMOS-Compatible Architectures

초록

Advances in semiconductor technology have been primarily driven by exponentially reducing the size of silicon transistors and pushing the quantum limit. However, continued scaling becomes extremely difficult in accordance with Moore's law. Conversely, recent advances in monolithic and heterogeneous integration by exploring non-group IV materials envision beyond CMOS scaling. This study entails the development of scalable van der Waals (vdW) integration technology by using all CMOS back-end-of-line-compatible processes: vertical 3D and lateral 2D integration of III-N devices, 2D materials (graphene and molybdenum disulfide), and CMOS. Advanced fluidic-assisted self-alignment transfer (FAST) provides a process accuracy of approximate to 32.6 nm as analyzed on a 200 mm wafer scale. The freestanding III-N chips are vdW integrated onto 2D materials, and the vdW interfaced multi-layer graphene successfully functioned as a back-gating interconnect line. Moreover, fidelity of the vdW interface is confirmed by conducting systematic yield, uniformity, and reliability analysis. The unique fourfold rotationally symmetric design of GaN transistors makes them compatible with massive and random FAST processing. GaN-based radio-frequency power and cascode GaN/Si transistors are integrated on silicon-on-insulator-CMOS. The proposed approach affords a remarkable advantage by surpassing the physical limits and facilitating functional diversification, thus advancing the concept of "More than Moore.

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