Low-power MPEG-4 motion estimator design for deep sub-micron multimedia SoC

초록

This paper proposes novel low-power MPEG-4 motion estimator with deep submicron technologies below 0.13 mu m. The proposed motion estimator reduces both dynamic and static power consumption so that it is suitable for large leakage process technologies. It exploits breaking-off search to reduce dynamic power consumption. To reduce static power consumption, block-wise shutdown method is employed. From the simulation results, power consumption was reduced to about 60%. The proposed motion estimator was designed in Verilog HDL and the estimated gate counts are about 45,000 gates.