INVESTIGATION OF THE POWER TRANSISTOR SIZE RELATED TO THE EFFICIENCY OF SWITCHING-MODE RF CMOS POWER AMPLIFIER

초록

In this work, we analyzed the efficiency of a switching-mode RF CMOS power amplifier with the following design parameters: the on resistance and the parasitic capacitance of the power transistor. The power amplifier is composed of a class-D type driver stage and a class-E type power stage. The power consumption of the driver stage, the load impedance of the power stage, and the loss of the output matching networks are considered for a numerical analysis. We investigated the normalized drain efficiency according to the variable supply voltage of the power stage for polar transmitter applications. From the simulated results of the power amplifier, we successfully proved the feasibility of using the numerical analysis. The designed power amplifier is implemented using 0.13 m RF CMOS process to verify the numerical results by means of an experiment. A distributed active transformer is used for an output matching network. (c) 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:110-117, 2014

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