A minimized test pattern generation method for ground bounce effect and delay fault detection

초록

An efficient board-level interconnect test algorithm is proposed considering both the ground bounce effect and the delay faults detection. The proposed algorithm is capable of IEEE 1149.1 interconnect test, negative ground bounce effect prevention, and also detects delay faults as well. The number of final test pattern set is not much different with the previous method, even our method enables to detect the delay faults in addition to the abilities the previous method guarantees.