Supporting ultra-low latency mixed-criticality communication using hardware-based data plane architecture

초록

Recent advances in embedded computing and networking technologies have led to a growing presence of Cyber-Physical Systems (CPS). An important trend is that recent CPS are typically composed of Mixed-Criticality (MC) systems that integrate multiple components with different criticality levels into shared networked systems and schedule them with different policies according to the system mode. In order to enable such MC scheduling, it is essential that CPS networking systems support mode detection and transition mechanisms. However, to the best of our knowledge, no study has focused on supporting such key mechanisms considering the crucial emerging CPS requirements: high bandwidth and ultra-low latency (ULL). To address this, we propose MC-HDP, an Ethernet-based CPS networking system that can provide such mode management mechanisms capable of meeting the ULL requirement (i.e., mu s-level). The proposed system extends Ethernet switches by employing hardware-based internal components, carefully designed to reduce and bound delay/overhead for mode detection and transition. Based on the system design, we derive an analytic delay bound for mode changes. For evaluation, we implemented a prototype of MC-HDP on top of NetFPGA-SUME and built a precise measurement environment using an in-house ULL packet generating tool. The evaluation result shows that MC-HDP achieves mu s-level mode change delay (i.e., up to 4.66 mu s in our setup), while the state-of-the-art mixed-criticality SDN and the standard SDN systems result in up to 2.63 and 117.2 ms of the mode change delays, respectively. The result proves that MC-HDP is highly effective in supporting the MC scheduling with ULL requirements, based on this improved mode change delay faster than the standard SDN by four orders of magnitude.

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