Input Balun Embedded Low-Noise Amplifier With a Differential Structure

초록

In this study, we designed a 5 GHz low-noise amplifier (LNA) with a differential structure using 0.18 mu m RFCMOS technology. An input balun is embedded into the LNA to enhance the gain, minimize the noise figure (NF), and miniaturize the overall chip size. The NF is minimized because the loss induced by the passive balun is removed. The first stage of the designed LNA performs the activities of the input balun and serves as the gain stage. To verify the feasibility of the proposed input-balun-embedded amplifier, we designed a typical LNA and the proposed LNA. We obtained a 29.4 dB gain with a NF of 1.85 dB. The measured dc power consumption is approximately 27 mW. The chip size is 1.0 x 0.74 mm(2). From the measured results of the typical and proposed LNAs, we successfully prove the feasibility of the proposed method to minimize the NF and enhance the gain.

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